By: Linus Torvalds (firstname.lastname@example.org), January 2, 2021 12: 21 pm
Jukka Larja (email@example.com) on January 1, 2021 10: 28 pm wrote:
> So yeah, I safe very mighty agree AMD has pleasant offering. ECC would not of direction matter right here though.
ECC fully matters.
ECC availability matters loads – precisely because Intel has been instrumental in killing your full ECC trade with or not it is horribly noxious market segmentation.
Hotfoot out and glimpse for ECC DIMMs – or not it is of direction laborious to search out. Yes – potentially entirely thanks to AMD – it can also merely had been gotten a runt bit greater lately, nonetheless that is precisely my point.
Intel has been detrimental to your full trade and to users due to the their noxious and misguided policies wrt ECC. Severely.
And in the occasion you safe not hang me, then lawful look at a few generations of rowhammer, where each and each time Intel and memory manufacturers bleated about how or not it may per chance per chance probably be fixed subsequent time.
Narrator: “No it wasn’t”.
And yes, that became – all all over again – entirely in regards to the misguided and arse-backwards coverage of “patrons safe not need ECC”, which made the marketplace for ECC memory plug away.
The arguments against ECC had been repeatedly full and snarl garbage. Now even the memory manufacturers are beginning safe safe ECC internally because they in the slay owned up to the fact that they fully comprise to.
And the memory manufacturers claim or not this is due to the economics and lower energy. And so they’re lying bastards – let me once extra demonstrate row-hammer about how those considerations comprise existed for several generations already, nonetheless these f*ckers fortunately sold broken hardware to patrons and claimed it became an “assault”, when it repeatedly became “we’re lowering corners”.
What number of occasions has a row-hammer take care of bit-flip came about lawful by pure noxious pleasant fortune on exact non-assault loads? We are capable of by no way know. Because Intel became pushing shit to patrons.
And I fully guarantee they came about. The “up to date DRAM is so estimable that it would not need ECC” became repeatedly a bedtime account for teenagers that had been dropped on their heads a runt bit too many occasions.
We’ve decades of irregular random kernel oopses that may per chance per chance by no way be defined and had been seemingly due to the noxious memory. And if it causes a kernel oops, I’m capable of make shuffle that there are several orders of magnitude extra circumstances where it lawful introduced on a runt bit-flip that lawful by no way ended up being so severe.
Yes, I’m pissed off about it. Yow will stumble on me complaining about this actually for decades now. I safe not must negate “I became correct”. I need this fixed, and I need ECC.
And AMD did it. Intel didn’t.
> I safe not of direction discover about AMD’s unofficial ECC