Dissecting the Apple M1 GPU, Part III

18 Apr 2021

Shadowy dice rendered on an Apple M1

After just a few weeks of investigating the Apple M1 GPU in January, I modified into as soon as in a plan to blueprint a triangle with my own launch source code. Even supposing I started dissecting the instruction position, the shaders there had been specified as machine code. A trusty graphics driver desires a compiler from high-level shading languages (GLSL or Steel) to a native binary. Our working out of the M1 GPU’s instruction position has evolved all the way during the final few months. Last week, I started writing a free and launch source shader compiler concentrated on the Apple GPU. Growth has been quick: at the pause of its first week, it would compile each and each traditional vertex and fragment shaders, ample to render 3D scenes. The spinning dice pictured above has its shaders written in idiomatic GLSL, compiled with the nascent free machine compiler, and rendered with native code bask in the first triangle in January. No proprietary blobs here!

Over the final few months, Dougall Johnson has investigated the instruction position in-depth, building on my preliminary work. His findings on the architecture are outstanding, focusing on compute kernels to complement my level of curiosity on graphics. Armed alongside with his notes and my tell stream tooling, I could per chance well chip away at a compiler.

The compiler’s affect must match into the advance context. Asahi Linux targets to whisk a Linux desktop on Apple Silicon, so our driver must nonetheless observe Linux’s most attention-grabbing practices bask in upstream building. That involves the inform of the Unique Intermediate Illustration (NIR) in Mesa, the dwelling for launch source graphics drivers. NIR is a delicate-weight library for shader compilers, with a GLSL frontend and backend targets including Intel and AMD. NIR is another option to LLVM, the compiler framework former by Apple. Correct because Apple prefers LLVM doesn’t indicate we have to. A bunch at Valve famously rewrote AMD’s LLVM backend as a NIR compiler, bettering efficiency. If it’s ethical ample for Valve, it’s ethical ample for me.

Supporting NIR as enter doesn’t dictate our compiler’s own intermediate representation, which displays the hardware’s affect. The instruction position of AGX2 (Apple’s GPU) has:

  • Scalar arithmetic
  • Vectorized enter/output
  • 16-bit kinds
  • Free conversions between 16-bit and 32-bit
  • Free floating-level absolute payment, dispute, saturate
  • 256 registers (16-bits every)
  • Register usage / thread occupancy trade-off
  • Some carry out of multi-peril or out-of-clarify (superscalar) execution

Every hardware property induces a compiler property:

  • Scalar sources. Don’t complicate the compiler by allowing unrestricted vectors.
  • Vector values at the periphery separated with vector mix and extract pseudo-directions, optimized out all the way through register allocation.
  • 16-bit devices.
  • Sources and locations are sized. The optimizer folds measurement conversion directions into uses and definitions.
  • Sources own absolute payment and dispute bits; directions own a saturate bit. Again, the optimizer folds these away.
  • A suited register file way working out of registers is uncommon, so don’t optimize for register spilling efficiency.
  • Minimizing register pressure is obligatory. Employ static single project (SSA) carry out to facilitate pressure estimates, informing optimizations.
  • The scheduler merely reorders directions with out leaking little print to the leisure of the backend. Scheduling is feasible each and each sooner than and after register allocation.

Inserting it collectively, a affect for an AGX compiler emerges: a code generator translating NIR to an SSA-based intermediate representation, optimized by instruction combining passes, scheduled to diminish register pressure, register allocated while going out of SSA, scheduled again to maximize instruction-level parallelism, and in the raze packed to binary directions.

These decisions replicate the hardware traits viewed to machine, which are themselves “shadows” forged by the hardware affect. Investigating these traits affords insight into the hardware itself. Imagine the register file. While every thread can gather entry to up to 256 half of-observe registers, there is a efficiency penalty: the extra registers former, the much less concurrent threads imaginable, since threads fragment a register file. The choice of threads allowed in a given shader is reported in Steel because the maxTotalThreadsPerThreadgroup property. So, we can survey the register pressure versus occupancy trade-off by reasonably just a few the register pressure of Steel shaders (confirmed through our disassembler) and correlating with the payment of maxTotalThreadsPerThreadgroup:


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